In many applications the functionality and/or speed of a central processing unit (CPU) is increased by interfacing the CPU to a separate computing circuit. When configured in this way, the CPU acts as a "host" for the separate computing circuit, delivering commands to the computing circuit and receiving responses therefrom. Often, the separate computing circuit includes one or more application specific integrated circuits (ASICs), which perform specific tasks. An ASIC may have a relatively simple structure of discrete logic circuits, or may be a highly complex structure, including one or more programmable circuits or CPUs, as is needed to perform the functions required by the host CPU.
ASICs are costly to design and costly to manufacture in small quantities. Accordingly, it is preferable for an ASIC to be compatible with a large number of host CPUs, so the same ASIC (potentially using different software) can be used in a number of applications, avoiding the need for repeated design effort, and increasing the quantities manufactured.
One difficulty that arises from the use of an ASIC with different host CPU's, is that various CPU families use substantially different methods for retrieving and storing data. Specifically, older CPU designs typically have an 8-bit data bus, for storing or retrieving eight bits to/from memory in parallel. For increased speed, more recent CPU designs utilize a 16-bit data bus for storing or retrieving sixteen bits to/from memory in parallel. Typically, 16-bit CPUs sold by a particular manufacturer are capable of executing software written for that manufacturer's prior 8-bit CPUs. Unfortunately, an ASIC configured for use with a 16-bit CPU typically cannot interface with an 8-bit CPU, and furthermore typically cannot interface with a 16-bit CPU when the 16-bit CPU is running 8-bit software.
Some CPU families, including the R2000, R3000 and R6000 RISC CPU's sold by Silicon Graphics, access memory by time-multiplexing address and data information on a common bus. Other CPU's, such as Intel and Motorola CPU's, access memory through separate address and data buses. As a result, an ASIC configured for use with a CPU having address and data buses will be incompatible with CPU's that multiplex address and data information on a common, time-multiplexed bus.